http://www.stevechamberlin.com/cpu A home-built CPU, and other messy electronics adventures Sun, 07 Mar 2010 20:27:08 +0000 http://backend.userland.com/rss092 en I'm having some trouble finding the best way to structure the Verilog code for this CPU. In particular, I've encountered one small headache and one larger one. The small headache relates to the best way to describe complex combinatorial logic that doesn't involve any registers. Consider some hypothetical logic that determines ... http://www.stevechamberlin.com/cpu/2010/03/07/verilog-headaches/ I've made a little bit of progress on the CPU in a CPLD project. As mentioned previously, this will be an 8-bit CPU with a 10-bit address space, targeting a 128 macrocell CPLD. The instruction set will be a simplified version of BMOW's, which itself was a close cousin of ... http://www.stevechamberlin.com/cpu/2010/03/03/cramming-everything-in/ OK, the CPU design spark is back, sooner than I'd expected. I have an urge to implement a minimal CPU using a CPLD. If you're not familiar with the term, a CPLD is a simple programmable logic chip, existing somewhere on the complexity scale between PALs (like the 22V10's I ... http://www.stevechamberlin.com/cpu/2010/02/28/a-cpu-in-a-cpld/ It works! I've continued poking away at this circuit to decode an RC airplane servo signal and trigger a camera shutter during flight, and I'm happy to report success! Once I switched to using the CD4013 flip-flop with a positive logic clear input instead of negative logic, it was a piece ... http://www.stevechamberlin.com/cpu/2010/02/25/rc-servo-signal-decoder-part-2/ Hey, I'm back. I think my oscilloscope made me do it. For the past six months I've been working with RC airplanes, not doing any electronics work. The oscilloscope has been taking up space on my desk while it sits untouched, gathering dust. Last week I finally decided I was ... http://www.stevechamberlin.com/cpu/2010/02/21/rc-servo-signal-decoder-for-camera-shutter-switch/ OK, it's time to admit defeat. 3D Graphics Thingy is not going to happen. It's been six months since I worked on it. Heck, I even let my web hosting account expire due to neglect. So what happened? I ran hard into the memory interface wall. Getting a decent DRAM controller ... http://www.stevechamberlin.com/cpu/2010/02/04/fail/ I think I'm making life more difficult than it needs to be, trying to get this DDR2 SDRAM interface to work. It's not that the logical interface is so complicated, really... you set your row and column addresses, do a burst transaction, check for refresh... not trivial, but not rocket ... http://www.stevechamberlin.com/cpu/2009/07/14/sdram/ Finally, some small progress on the memory interface. After banging my head every which way against the Xilinx tools, and reading everything I could find on the subject, I came across Leo Silvestri's page on modifying the Xilinx MIG memory controller design for a Spartan 3E board. It's for a ... http://www.stevechamberlin.com/cpu/2009/07/05/small-progress/ I think I'm about ready to crush this Xilinx starter kit under my boot, and use the pulverized component dust to scrub my toilet. That's not quite fair, though, as my frustration isn't really with the hardware, but with the inexplicable Xilinx software. At this point, I've spent about 20 ... http://www.stevechamberlin.com/cpu/2009/07/03/xilinx-memory-controller/ I've been working hard the past week on a DDR2 memory controller for the Xilinx starter kit, and refining my estimates for 3d Graphics Thingy's memory bandwidth requirements. There's been progress, but it feels like things are moving at a snail's pace. I wrote earlier about some basic bandwidth estimates, and ... http://www.stevechamberlin.com/cpu/2009/06/27/more-on-memory/