Technical Info
Big Mess O’ Wires is an original CPU design. It borrows liberally from other homebrew designs, as well as the MAYBE design presented in the book Computation Structures by Stephen Ward and Robert Halstead. Data busses are 8 bits wide, and the address bus is 24 bits. Four 8-bit registers are used for general data, and three 24-bit registers store the program counter, stack pointer, and a scratch/working address pointer. Registers and the arithmetic and logic unit are interconnected by one data bus, while RAM, ROM, and memory-mapped hardware devices use a second data bus. The ALU also has dedicated left and right data input busses.
Machine language instructions are implemented as a series of micro-instructions, stored in three parallel ROMs to create a 24-bit microcode word. One micro-instruction is executed each clock cycle, and the micro-instruction bits are used directly as enable and select inputs to control the 50 or so chips in the machine. Up to 16 micro-instructions may be needed to implement a single machine language instruction.
24-bit addresses allow for up to 16MB of memory, but only 512K or 1MB is installed. The most-significant byte of the address is called the bank byte, and is normally invisible to programs. The standard instruction set presents a 16-bit interface to programs, so each one runs inside its own private 16-bit (64K) address bank, unaware and unaffected by other programs in other banks. The operating system code in bank zero is able to use full 24-bit addressing instructions, in order to provide system services and swap between active processes to create a multi-tasking runtime environment.
A 16K ROM contains the OS boot program, and is mapped into bank zero. A USB-to-TTL interface based on an FTDI chip provides an easy way to move data to and from a Windows PC. A standard PC keyboard with PS/2 connector is used for keyboard input, and a 20×4 character text LCD serves as the output display.
BMOW is built on an Augat wire-wrap board pre-populated with thousands of wire-wrap pins. The chips are pushed into the board without soldering, and can be easily removed, similar to a prototyping breadboard. Unlike a breadboard, the pins are individually connected on the underside of the board according to the needs of the circuit design. A wire-wrap tool is used to wrap stripped wire ends tightly around each pin. Wires can be removed fairly easily in case of a mistake. BMOW contains about 1000 such wire wraps.
BMOW is still a work in progress. Currently most of the hardware construction is complete, but there is still much work to be done on the development tools and OS software. Audio and video outputs may also be added in the future.
Technical Documents
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Hi, Steve.
Thanks for coming up with the idea of doing a homebrew 6502-compatible cpu! I spent many enjoyable hours programming on an Apple IIe.
A couple questions around the GAL equations, and then a generic question, from a complete beginner to the idea of designing your own cpu.
GAL questions :
What exactly does GAL stand for?
What tool(s) did you use to process the GAL equations?
Is there any documentation you can refer me to for the language used to write these GAL equations?
General question :
Elsewhere you mentioned that you wrote some Verilog code to prove-out your design of bmow. Could you post your Verilog code, and any supplemental Verilog testbenches?
Some questions on the microcode source :
Is it written in a standard language, or a language of your own design to suit your needs?
If the code is written in some standard language, what is the name of this language, where can I find some documentation on it, and what tool(s) are used to process it?
Hi John. BMOW isn’t exactly 6502-compatible. With the current microcode, it implements a machine language instruction set very similar to the 6502, but it lacks zero page addressing for example. Still, it’s close enough that I’ve been able to use some 6502 development tools. With different microcode, I could probably emulate the Z80 or 8080 instruction set too. You can still buy new 6502’s from electronics distributors, if your goal is mostly to do some 6502 hacking. I was more interested in the CPU design itself, but I used what I knew of the 6502 as a general guide.
GALs are reprogrammable PALs, and are a precursor to modern programmable logic devices like FPGAs. You can read more about them in an article I wrote for uCHobby. The EQN equation files are processed by a tool called EQN2JED, which I found as part of the Opal Jr. tool distribution. Try here for docs. The tools themselves are here.
I’ll post my Verilog code, but it’s mostly a big mess, and doesn’t exactly match the current hardware.
The microcode is a language of my own design, processed by a tool of my own. The language should hopefully be self-explanatory, if you’ve looked at the BMOW system block diagrams. Each machine language instruction is a series of up to 16 microinstruction phases, and each microinstruction does a simple move of a byte between memory or registers. In some cases there are several possible microinstructions for the same phase, and the one to use is determined by the current value of the condition codes.
You’re welcome to email me if you have other questions.
Hey, Steve.
Thanks for responding, and thanks for the ptr to the article, re : GALs! I read it and it answered all my questions - wonderful article!
I too am interested in cpu design (currently a sophomore-year Computer Engineering major). My goal right now is doing a self-directed search of what other hardware-hackers have already done in the area of cpu design, to read about and learn from the experiences of others. I suspect I’ll be asking more questions, once I know a little more